I only found this comment in the source file:
> /* For performance, all the general caches are L1 aligned.
> * This should be particularly beneficial on SMP boxes, as it
> * eliminates "false sharing".
> * Note for systems short on memory removing the alignment will
> * allow tighter packing of the smaller caches. */
To avoid false sharing we would need SMP_CACHE_BYTES aligning, not L1
aligning.
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