> (hm, dont we have an assert in there to catch ISA IRQs bound to the second
> IO-APIC?) In any case, it would be a very surprising move if anyone added
> a second IO-APIC for the sake of *ISA* devices. This would be truly
> backwards.
It's just the matter of the order I/O APICs are listed in the MP table.
I think it's only the limited number of multiple-I/O APIC systems
available so far that prevented from a reverse listing to happen. Given
recent developments which lead to more such systems (e.g. using the
infamous ServerWorks chipset which embeds two I/O APICs internally), it's
only the matter of time until this happens, I'm afraid.
No need to hurry, though -- we might fix the problem once (if) it
appears.
-- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org Please read the FAQ at http://www.tux.org/lkml/