Re: VT82C686A corruption with 2.4.x

[Byron Stanoszek]

On Thu, 1 Feb 2001, Vojtech Pavlik wrote:

> On Thu, Feb 01, 2001 at 11:46:08AM -0500, Byron Stanoszek wrote:
> 
> > Yeah, by bios does the same thing too on the Abit KT7(a).
> 
> Ok, I'll remember this. This is most likely the cause of the problems
> many people had with the KT7 in the past.

What cause are you referring to? As far as I know, there are two options to
increasing the FSB clock.. one increases both FSB+PCICLK, the other just
increases FSB. If you increase the FSB only, it should keep PCICLK at a solid
33. (But I could be wrong, I've never tested that. I can tomorrow though.)

> The U33 chips do UDMA timing in PCICLK (T = 30ns @ 33MHz) increments, U66 in
> PCICLK*2 (T = 15ns @ 33 MHz) increments, and for U100 it's assumed that
> there is an external 100MHz clock fed to the chip, so that the UDMA timing is
> in T = 10ns increments independent of the PCICLK. I'm not 100% sure about
> the last, it might be just PCICLK*3 (T = 10ns @ 33 MHz). An experiment needs
> to be carried out to verify this.

I don't have a KT7A personally, I only have a KT7. Can anyone else with a KT7A
verify this? By verify, I take it you mean to use idebus=33 and overclock
PCICLK? :) At least that would determine if UDMA100 is based on PCI or an
external 100MHz source.

Regards,
 Byron

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