Nope. There's a table explaining how page flags and MTRRs interact in
the Intel x86 manual, volume 3 (it's in section 9.5.1 "Precedence of
Cache Controls" in the fairly recent edition I have here).
For example, with PCD set, PWT clear, and the MTRRs saying WC, the
effective memory type is WC. In addition, there's a note saying this
may change in future models. So you have to set PCD | PWT if you want
to get uncached in all cases.
David Wragg
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