It doesn't _have_ to be.
But think like a good hardware designer.
In 99% of all cases, where do you want the results of a read to end up?
Where do you want the contents of a write to come from?
Right. Memory.
Now, optimize for the common case. Make the common case go as fast as you
can, with as little latency and as high bandwidth as you can.
What kind of hardware would _you_ design for the point-to-point link?
I'm claiming that you'd do a nice DMA engine for each link point. There
wouldn't be any reason to have any other buffers (except, of course,
minimal buffers inside the IO chip itself - not for the whole packet, but
for just being able to handle cases where you don't have 100% access to
the memory bus all the time - and for doing things like burst reads and
writes to memory etc).
I'm _not_ seeing the point for a high-performance link to have a generic
packet buffer.
Linus
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