581365-8 Computer Organization II, Course exam 14.12.2010  

You may answer in English, Finnish, or Swedish.
Write in each answer sheet your name, signature, id-number, course name, and page nr/total nr of pages.
Write down any assumptions you need to make. One or two page answer is sufficient for each problem.

1. [10 p] Two-way set-associative write-back cache. Assume a read reference to variable Top in (linear, physical) memory address 0x2345ABC0. Assume that cache is full.
   1. [5 p] Where in the cache may the value for variable Top be located? How does the cache know, if Top is in the cache or not?
      
   2. [5 p] What happens in the system, if Top is not in cache? Which cache implementation policies are involved and what happens because of them?


2. [10 p] Pipeline. Assume 5-stage pipeline.
   1. [4 p] Give machine language examples for the following dependencies (hazards): (i) read-after-write, (ii) write-after-read, (iii) control. Explain what type of problems the dependencies would cause in the pipeline unless they were solved.
   2. [3 p] Give three different solution methods for read-after-write dependencies. Explain why each solution works.
   3. [3 p] Explain dynamic branch prediction. What problem does it solve? How does it work? Use the 5-stage pipeline to illustrate the problem and its solution.
       
3. [10 p] Control.
   1. [5 p] Show (i) micro-operations and (ii) control signals for the processor in Figure 15.5 (below) for the fetch-execute instruction cycle (ignore indirect cycle and interrupt cycle) for the MUL instruction:
             MUL Y      ; multiply contents of AC by the value of variable Y
   2. [5 p] How would the control signals for the instruction cycle (again ignore indirect cycle and interrupt cycle) be generated with horizontal micro-programming? Use the "MUL Y" instruction above as your example and show, when and how all the control signals for that instruction are generated.