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Computer Organization II, Spring 2010, Exercise 6

These homework exercises will be covered in practice session on Wednesday 24.2.2010.

This sixth week's homework covers computer Superscalar processing and the Control Unit (Sections 14-17, older editions sections 14, 16-17).

The last topic, Parallel organization and multicore, is not covered in exercises. If you have any questions about those, please do not hesitate to ask in the meeting.

SPECIAL TASK:

Submission on paper (1-2 pages) on Wednesday 24.2.2010 during the exercise meeting.

1. Learning diary

   Continue maintaining the learning diary through out the course.

   This weeks submission should cover the issue in your diary after the previous submission.

   You could reflect the course content with your earlier knowledge, point out the interesting and not so interesting areas.

   Think about the course as a whole: what issues would you omit from the course, which should be coveered in more details, are there topics that were missing totally. Please justify your claims.

2. Article

   This weeks submission is about the computer architecture. You may select one of these articles as the base of your text

   1. C. Webb: IBM z10: the next-generation mainframe microprocessor. IEEE Micro, March-April 2008, pp. 19-29
      OR
   2. J. Andrews and N. Baker: Xbox 360 system architecture. IEEE Micro, March-April 2006, pp. 25-37

   The IEEE Micro's March/April issue each year seems to be a special issue on new processor architectures. These articles are from different years and the processors are targeted for different markets.

   Write a paper (appr. 1 page, 1500-2000 characters.) in which you compare the architectural of the selected processor with a 'standard' desktop computer as covered in the course. What differences there are and why? What similarities? What was the most surprising feature of the architecture? The paper must describe your opinion and viewpoint very clearly. A reference of the architecture is not enough. The focus must be in the comparison.

HOMEWORK:

1. In-order vs out-of-order, Problem 14.6.

   Figure 14.14. shows an example of a superscalar processor organization. The processor can issue two instructions per cycle, if there is no resource conflict and no data dependence problem. There are essentially two pipelines, with four processing stages (fetch, decode, execute and store). Each pipeline has its own fetch, decode, and store unit. Four functional units (multiplier, adder, logic unit, and load unit) are available for use in the execute stage and are shared by the two pipelines on a dynamic basis. The two store units can be dynamically used by the two pipelines, depending on availability at a particular cycle. There is a lookahead window with its own fetch and decode logic. This window is used for instruction lookahead for out-of order instruction issue. Consider the following program to be executed on this processor:

               I1: Load R1, A        /R1 < - Memory(A) /
               I2: Add R2, R1        /R2 < - R(2) + R(1) /
               I3: Add R3, R4        /R3 < - R(3) + R(4)
               I4: Mul R4, R5        /R4 < - R(4) * R(5) /
               I5: Comp R6           /R6 < - R(6) /
               I6: Mul R6, R7        /R6 < - R(6) * R(7) /
   

   1. What dependences exist in the program?
   2. Show the pipeline activity for this program in the processor of Figure 14.14. using in-order issue with in-order completion policies and using a presentation similar to Figure 14.2.
   3. Repeat for in-order issue with out-of-order completion.
   4. Repeat for out-of-order issue with out-of-order completion.

2. Register renaming, Problem 14.4.
   1. Identify the data dependency (RAW), antidependency (WAR) and output dependency (WAW) in the following instruction sequence:

                  I1: R1 = 50
                  I2: R1 = R3 + R4
                  I3: R2 = R4 - 10
                  I4: R4 = R1 + R2
                  I5: R2 = R1 + 45
      

   2. Rename the registers from part a to prevent dependency problems. Identify references to initial register value using the subscript "a" to the register reference.

3. Micro-operations and ALU, Problem 15.1.

   Your ALU can add two input registers, and it can logically complement the bits of either input register, but it cannot subtract. Numbers are to be stored in twos complement representation.

   1. List the micro-operations your control unit must perform to cause a subtraction.
   2. Would it be more convenient to use sign-magnitude representation instead?

4. Micro-operations and control signals, Problem 15.2.

   Show the micro-operations and control signals in the same fashion as Table 15.1 for the processor in Figure 15.5 for the following instructions

   • Load Accumulator
   • Store Accumulator
   • Add to Accumulator
   • AND to Accumulator
   • Jump

5. Control-memory, Problem 16.4.

   Consider the control unit of Figure 16.7. Assume that the control memory is 30 bits wide. The control portion of the microinstruction is divided into two fields. A micro-operation field of 15 bits specifies the micro-operation to be performed. An address selection field specifies a condition, based on the flags, that will cause a microinstruction branch. There are eight flags.

   1. How many bits are in the address selection field?
   2. How many bits are in the address field?
   3. What is the size of the control memory?

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Tiina.Niklander@cs.helsinki.fi