Computer Organization II, Spring 2010, Exercise 3
These homework exercises will be covered in practice session on Wednesday 3.2.2010.
This third week's homework covers cache and memory (Sections 4, 5.1, 5.3 and 8.3-8.5).
SPECIAL TASK:
No submission this week. Next submission on Wednesday 10.2.2010.
- Learning diary
Continue maintaining the learning diary. At least write down issues you have learned and issues that still need to be studies more. Remember to write down also the times used to study this course.
- Article
L. Peng et.al.: Memory hierarchy performance measurement of commercial dual-core desktop processors. Journal of Systems Architecture 54(2008) 816-828. (publisher Elsevier)
Again, locate the article before the meeting.
HOMEWORK:
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Problem 4.12:
Concider a computer with the following characteristics: total of 1Mbyte of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes.- For the main memory addresses of C101E, 01234, and F0B30, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache.
- Give any two main memory addresses with different tags that map to the same ceche slot for a direct-mapped cache.
- For the main memory addresses of C101E and F0B30, give the corresponding tag and offset values for a fully-associative cache.
- For the main memory addresses of C101E and F0B30, give the corresponding tag, cache set, and offset values for a two-way set-associative cache.
- Intel 80486
- Problem 4.9 [Stal09 and Stal06] (4.8 [Stal03]) (4.14 [Stal99])
- Give also an example on situation where the approximation does not work (I.e., cache line A is replaced even though line B was referred to longer time ago). Why does it not work?
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Problem 4.23:
Consider a cache with a line size of 64 bytes. Assume that on average 30% of the lines in the cache are dirty. A word consists of 8 bytes.- Assume there is a 3% miss rate (0.97 hit ratio). Compute the amount of main memory traffic, in terms of bytes per instruction for both write-through and write-back policies. Memory is read into cache one line at a time.
- Repeat part a for a 5% rate.
- Repeat part a for a 7% rate.
- What conclusion can you draw from these results?
NOTE: The calculation is easier if you think about a set of 100 instructions. Each instruction must be read and during their execution each of them access (read or write) the memory again. 20% of the instruction can be assumed to be writes.
- Problem 8.6 [Stal09 and Stal06] (8.4 [Stal03]) (7.4 [Stal99])
- Calculations
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Problem 8.14 [Stal09 and Stal06]
(8.9 [Stal03]) (7.9
[Stal99])
A Computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 15 ns are required to access it. If it is in main memory but not in the cache, 50 ns are needed to load it into the cache, and then the reference is started again. If the word is not in main memory, 10 ms are required to fetch the word from disk, followed by 50 ns to copy it to the cache and then the reference is started again. The cache hit ratio is 0.9 and the main-memory hit ratio is 0.5. What is the average time in ns required to access a referenced word in this system? - Problem 4.20:
- Consider a L1 cache with an access time of 1 ns and a hit ratio of H=0.9. Suppose that we can change the cache design (size of cache, cache organization) such that we increase H to 0.95, but increase access time to 1.2 ns. What conditions must be met for this change to result improved performance?
- Explain why this result makes intuitive sense.
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Problem 8.14 [Stal09 and Stal06]
(8.9 [Stal03]) (7.9
[Stal99])
Self-study:
If you feel that you would like to have more exercise with the memory addressing and set-associative cache, please follow the link. I have created a simple set of questions, that hopefully help you in understanding the address handling in set-associative cache.