University of Helsinki Department of Computer Science
 

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Computer Organization II, Spring 2009, Exercise 6

These homework exercises will be covered in the last practice session on week 17 (In Finnish Thu 23.4, In English Fri 24.4).

Each week one article-based question must be submitted on paper to the teacher.

You need (at least to try hard) to solve the questions in advance, that is before the meeting. In the meeting we will discuss about the questions and their solutions. There is no time to solve them there. Solutions to the homework are not provided afterwards.

This sixth week's homework covers RISC and Superscalar pipelining (Sections 13 and 14).

ARTICLE:

Return the answer on paper in the meeting.

J. Andrews and N. Baker: Xbox 360 system architecture. IEEE Micro, March-April 2006, pp. 25-37

Xb0x is a video game device. The article expains its architecture. Write a paper (appr. 1 page, 1500-2000 characters.) in which you compare the architectural choises of xbox with a 'standard' desktop computer. What differences there are and why? What similarities? The paper must describe your opinion and viewpoint very clearly. A reference about either architecture is not enough. The focus must be in the comparison.

Please remember to put your name on the returned paper.

HOMEWORK:

  1. Problems 13.4 "Reorganize the code seguence in Figure 13.6d to reduce the number of NOOPs." and 13.8 [Sta06] ( 13.6 [Sta03]) " Add entries for the following processors to Table 13.7 (Table 13.8) a) Pentium II, b) PowerPC."

  2. Problem 13.6 [Sta06] (13.5 [Stal03], 12.5 [Stal99])

  3. Problem 13.7 [Sta06]:
    A RISC machine may do both a mapping of symbolic registers to actual registers and a rearrangement of instructions for pipeline efficiency. An interesting question arises a to the order in which these operations should be done. Consider the following program fragment:
                LD     SR1, A
                LD     SR2, B
                ADD    SR3, SR1, SR2
                LD     SR4, C
                LD     SR5, D
                ADD    SR6, SR4, SR5
    
    1. First do the register mapping and then any possible instruction reordering. How many machine registers are used? Has there been any pipeline improvement?
    2. Starting with the original program, now do the instruction reordering and then any possible mapping. How many machine registers are used? Has there been any pipeline improvement?

  4. Problems 14.3 and 14.5 [Sta06] (14.3 and 14.5 [Sta03], 13.3 and 13.5 [Sta99]

  5. Problem 14.6 [Stal06]          (14.6 [Stal03], 13.6 [Stal99])
    Please note, that the comment fields given for instructions (I4) and (I6) are wrong.


Tiina.Niklander@cs.helsinki.fi