Computer Organization II, Spring 2009, Exercise 5
These homework exercises will be covered in practice session on week 16 (In Finnish Thu 16.4, In English Fri 17.4).
Each week one article-based question must be submitted on paper to the teacher.
You need (at least to try hard) to solve the questions in advance, that is before the meeting. In the meeting we will discuss about the questions and their solutions. There is no time to solve them there. Solutions to the homework are not provided afterwards.
This fifth week's homework covers Instruction sets and processor structure (Sections 10-12).
ARTICLE:
Return the answer on paper in the meeting.
This week you have two alternatives:
Same as last week C. Webb: IBM z10: the next-generation mainframe microprocessor. IEEE Micro, March-April 2008, pp. 19-29.
OR graphics processor related paper K. Fatahalian and M. Houston: A Closer Look at GPUs. CACM 51(10), October 2008, pp. 50-57
Focus your report (1/2 - 1 page) on pipelining of the selected paper.
Explain the pipelining in your own words. Make sure that you cover
issues like how many stages, main purpose of each stage, issues related to
data or operand processing.
Please remember to put your name and the name of the article on the returned report.
HOMEWORK:
- Problems 10.6 and 11.18 [Stal06]
(10.3 and 11.12 [Stal03]) (9.3 and 10.11 [Stal99])
You may assume that each instruction set has a DIV instruction. Three address instruction sets have naturally three operands. Also assume, that variables A, B, C, D, E, F and X are in memory.
(missprint in the very old text book [Stal99], see http://www.cs.helsinki.fi/u/kerola/tikra/coa_errata/errata.txt).
- Problem 10.17 [Stal06] (10.9 [Stal03]) (9.7 [Stal99])
- Problem 11.7 [Stal06]
(11.6 [Stal03]) (10.5 [Stal99])
Give also example instruction for parts (a) and (b).
Would is be worthwhile in the instruction to place the opcode only after the operands? Why? - Problem 12.13 [Stal06]
(12.5 [Stal03]) (11.5 [Stal99])
Also,- Give an example on situation, where the algorithm in Figure 12.17 [Stal06] (12.17 [Stal03]) (11.16 [Stal99]) would be better than the two other alternatives.
- Give an example on situation, where the left side algorithm in Figure 12.25 [Stal06] (12.25 [Stal03]) (11.24 [Stal99]) would be better than the two other alternatives.
- Give an example on situation, where the right side algorithm in Figure 12.25, [Stal06] (12.25 [Stal03]) (11.24 [Stal99]) would be better than the two other alternatives.
Missprint in the very old book: the left side state diagram in Figure 11.24 [Stal99] of the very old text book has a typo: lower leftmost state should be "Predict Taken".
- Pipeline and branching
- Assume a pipeline with 4 stages: fetch instruction (FI), decode
instruction and calculate address (DA), fetch operand (FO), and execute
(EX). Draw a diagram (see slide 18 six-stage pipeline) for a sequence of
7 instructions, in which the third instruction is a branch that is taken
and in which there are no data dependencies.
- A computer with five-stage pipeline deals with conditional branches by stalling for the next three cycles after hitting one. How much does stalling hurt the performance if 20% of all instructions are conditional branches? Ignore all sources of stalling except conditional branches.
- Assume a pipeline with 4 stages: fetch instruction (FI), decode
instruction and calculate address (DA), fetch operand (FO), and execute
(EX). Draw a diagram (see slide 18 six-stage pipeline) for a sequence of
7 instructions, in which the third instruction is a branch that is taken
and in which there are no data dependencies.