Computer Organization II, Spring 2009, Exercise 2
These homework exercises will be covered in practice session on week 12 (Fri 20.3).
Each week one article-based questions must be submitted on paper to the teacher.
You need (at least to try hard) to solve the questions in advance, that is before the meeting. In the meeting we will discuss about the questions and their solutions. There is no time to solve them there. Solutions to the homework are not provided afterwards.
The weekly meetings are important for your learning. They give you structure for the course and support you in learning the content. They also give you some hints about the exam.
During the meeting, you will also have possibility to ask about the parts you feld were difficult to understand. This is your opportunity to make sure that you master the material well.
This first week's homework covers the computer overview and bus.
ARTICLE:
Return the answer on paper in the meeting.
Look at the article: R. Lu and C.-K. Koh, Samba-bus: a high performance bus architecture for system-on-chips. In proceedings of the international conference on Computer Aided Design (ICCAD'03). ACM, 2003, pp. 8-12
The article explains a new bus architecture.
Please write (In Finnish or in English) a short (1/2 -1 page) 'essay' about the topic. Some themes that you could (alternatively) use in your essay:
- How feasible do you think this solution is? Why?
- (or Explain why (and how) the non-winner is still allowed to access the bus?)
There is no need for you to agree with the article. You can also argue against the article.
Please notice that you need not read and memorize the article. You just need to be able to make your own opinion about the content. You may be critical about the content.
HOMEWORK:
- Hardware support for operating system. It is difficult to
make a reliable operating system (such that the applications can not
disturb each other or use other's resources without permission), if one
does not get some (processor) hardware support for it. What types of
services (support) does the processor hardware offer for this purpose
- in memory management?
- in process management?
- in device management?
- in resource managament?
- I/O.
NOTE: Change to Problem 3.5 in Spring 2010 - Explain term memory-mapped I/O and how is it implemented? What would be an alternative for it?
- What does DMA mean and how is it implemented? What would be an alternative for it?
- Problems 3.9 and 3.19 [Stal06] (3.8, 3.10 [Stal03]) (3.7, 3.9 [Stal99])
- Problem 3.8 [Stal06]
(3.7 [Stal03]) (3.6 [Stal99])
- How does one prevent two devices to act simultaneously as Bus Masters, when they both try to use the bus at the same time? Who makes the decision? Which device (or devices) get the turn? How does one know that it got the turn?
- What determines, how many devices can be attached to the bus?
- PCI-bus.
- Assume that the memory circuit can locate the target data in
one, two
or 3 clock cycles. How does the memory circuit tell this to the
CPU?
See Fig 3.23 [Stal06] (Fig 3.23 [Stal03]) (Fig 3.22 [Stal99]) - Assume that the last data set has only 1 byte of data even though the data bus is 32 bits wide. Who determines which 8 wires are used to transmit that byte? When and how that information is given to the other party?
- What happens if three devices want simultaneously use the bus? Who makes the decision? Which device (or devices) get the turn? How does one know that it got the turn? Will signals get crossed, when all devices have the REQ-pin at the same location?
- Assume that the memory circuit can locate the target data in
one, two
or 3 clock cycles. How does the memory circuit tell this to the
CPU?