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Computer Organization II,  Fall 2001, HW 2

1. Problems A.4 and A.6 from the book (p. 707)

    

2. [2 HWP] Problem A.8 from the book (overall picture and Z3 details)
   Give also a Kranaugh map for the SOP presentation, and use it the get an optimized SOP presentation for Z3.
   
   
3. Problem 4.10 from the book (p. 144)

    

4. [2 HWP] Processor has a unified write back cache. Its hit ratio is 98%. Each instruction has, in average, 1.4 memory references (instruction plus 0.4 data references). Cache line is 4 words. There is bus transaction with which one can read or write whole cache line in 50 clock cycles (CPU cycles). To read or write one word takes 30 clock cycles. About 20% of the cache blocks have been written onto. To execute one instruction it takes in average 5 clock cycles plus the time for those data items that are not found in cache. During a cache miss the processor is waiting. The processor executes one instruction at a time.  
   1. How many clock cycles per instruction is needed, in average, for this processor?
   2. How many clock cycles per instruction would be needed, in average, for this processor, if there were no cahce?