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Computer Organization II,  Fall 2001, HW 1

1. I/O.
   1. Explain term memory-mapped I/O?
   2. What other possibilities are there to implement I/O than memory-mapped I/O?
   3. Why would memory mapped I/O be better than its alternative(s)?
   4. How can one implement a system where user level processes can not mess up data structures used in memory mapped I/O, by accident or in purpose? Give at least two possible solutions.
      
2. User state and priviledged state
   1. Give three different types of situations where processor state changes from user state to priviledged state.
   2. Give three different types of situations where processor state changes from priviledged  state to user state.
   3. What use is there from the priviledged state? What bad?
   4. Whould it be useful to offer multiple levels of priviledged states? Why?

    

3. Problems  3.7 and 3.8 from the book (p. 91). The latter one may need a little bit of thinking.

    

4. In Figure 3.19 CPU READ operation is shown both with synchronic and asynchronic timing. Give the corresponding figures for CPU WRITE operation. You may assume that the bus has a Write signal and its use is analogous to the use of the Read signal. Give reasoning for each signal level change for each signal.

    

5. PCI-bus.
   1. Assume that the memory circuit can locate the target data in one, two or 3 clock cycles. How does the memory circuit tell this to the CPU? (See Fig. 3.22)
   2. Assume that the last data set has only 1 byte of data even though the data bus is 32 bits wide. Who determines which 8 wires are used to transmit that byte? When and how that information is given to the other party?
   3. What happens if three devices want simultaneously use the bus? Who makes the decision? Which device (or devices) get the turn? How does one know that it got the turn?