Computer Organization II,  Autumn 2010, HW 3

1. Problem 4.12 [Stal10 and Stal06]          (4.10 [Stal03])
   Note: Different editions have different main memory addresses. Use addresses C101E, 01234, and F0B30 [Stal10].
    
2. Problem 4.9 [Stal10 and Stal06]          (4.8 [Stal03])
   1. Give also an example on situation where the approximation does not work (I.e., cache line A is replaced even though line B was referred to longer time ago). Why does it not work?
       
3. Problem 4.23 [Stal10 and Stal06]          (-- [Stal03])
   Consider a cache with a line size of 64 bytes. Assume that on average 30% of the lines in the cache are dirty. A word consists of 8 bytes. Assume also, that 32% of the instructions are writes.
   1. Assume there is a 3% miss rate (0.97 hit ratio). Compute the amount of main memory traffic, in terms of bytes per instruction for both write-through and write-back policies. Memory is read into cache one line at a time.
   2. Repeat part a for a 5% rate.
   3. Repeat part a for a 7% rate.
   4. What conclusion can you draw from these results?

   NOTE: The calculation is easier if you think about a set of 100 instructions. Each instruction must be read and during its execution it will access (read or write) the memory again. Once you get the count of average bytes needed for 100 instructions, it is easy to count number of bytes needed for 1 instruction.

4. Problem 8.6 [Stal10 and Stal06]          (8.4 [Stal03]) 
    
5. Performance calculations
   1. Problem 8.14 [Stal10 and Stal06]           (8.9 [Stal03]) 
      
   2. Problem 4.20 [Stal10]           (4.20 with different constants, use those below) [Stal06], -- [Stal03]) 
      1. Consider a L1 cache with an access time of 1 ns and a hit ratio of H=0.9. Suppose that we can change the cache design (size of cache, cache organization) such that we increase H to 0.95, but increase access time to 1.2 ns. What conditions must be met for this change to result improved performance?
      2. Explain why this result makes intuitive sense.